MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
(5) Data Slice Line Specification Circuit
Selection of field to be sliced data
1
Specification of data slice line
In the case of the main data slice line, the field to be sliced data is
selected by bits 2 and 1 of the data slicer control register 1 (address
00EA16). In the case of the sub-data slice line, the field is selected
by bits 2 and 1 of the data slicer control register 3. When bit 2 of
the data slicer control register 1 is set to “1,” it is possible to slice
data of both fields (refer to Figures 32 to 34).
M37274MA-XXXSP has 2 data slice line specification circuits for
slicing arbitrary 2 Hsep in 1 field. The following 2 data slice lines
are specified .
<Main data slice line>
This line is specified by the caption position register (address
00E016).
3
Specification of line to set slice voltage
<Sub-data slice line>
The reference voltage for slicing (slice voltage) is generated by
integrating the amplitude of the clock run-in pulse in the particular
line (refer to Table 4).
This line is specified by the data slicer control register 3 (address
00EB16).
4
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register (in case of
the sub-data slice line, by bits 3 to 7 of the data slicer control register
3), this Hsep is sliced.
Field determination
The field determination flag can be read out by bit 5 of the data
slicer control register 1. This flag charge at the falling edge of
Vsep.
The values of “0016” to “1F16” can be set in the caption position
register. Bit 7 to bit 5 are used for testing. Set “1002.” Figure 38
shows the signals in the vertical blanking interval. Figure 39 shows
the structure of the caption position register.
Vertical blanking interval
Video signal
Composite
video signal
V
sep
sep
Line 21
H
Count value to be set in the caption position register (“11 16” in this case)
Magnified
drawing
H
sep
Clock run-in
Start bit + 16-bit data
Start bit
Composite video
signal
min. max.
Time to be set in the
start bit position register
Fig. 38. Signals in Vertical Blanking Interval
43
RENESAS [ RENESAS TECHNOLOGY CORP ]
