MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR1 area (addresses E016 to FF16
)
<Bit allocation>
<
State immediately after reset >
:
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
:
Name
: No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
State immediately after reset
b0 b7 b0
b7
Caption position register (CP)
E116 Start bit position register (SP)
E016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
1
0
0 CP4CP3 CP2 CP1CP0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
E216
E316
Window register (WN)
0
SSL7
0
0
WN5 WN4 WN3 WN2 WN1 WN0
Sync slice register (SSL)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
0
0
0
1
0
1
E416
E516
E616
CR13 CR12 CR11 CR10
CR21
Clock run-in register 1 (CR1)
0
1
1
0
0
0
1
1
Clock run-in register 2 (CR2)
Clock run-in detect register 1 (CRD1)
1
1
1
E716
E816
E916
EA16
EB16
EC16
CRD17CRD15 CRD15 CRD15 CRD15
Clock run-in detect register 2 (CRD2)
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
CRD27CRD25 CRD25 CRD25 CRD25 CRD22CRD21 CRD20
DSC17
DSC27
DSC15
DSC25
DSC12 DSC11 DSC10
DSC22DSC21 DSC20
?
?
0
0
?
?
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
Caption data register 3 (CD3)
Caption data register 4 (CD4)
A-D conversion register (AD)
A-D control register (ADCON)
Timer 1 (TM1)
0016
0016
?
ED16
EE16
EF16
F016
ADVREF ADSTR
ADIN1 ADIN0
ADIN2
0
0
0
?
0
0
1
0
0
0
FF16
0716
FF16
0716
0016
0016
Timer 2 (TM2)
Timer 3 (TM3)
Timer 4 (TM4)
F116
F216
F316
F416
F516
F616
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
2
D5 D4 D3 D2 D1 D0
D7 D6
I C data shift register (S0)
?
0016
2
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
F716 I C address register (S0D)
2
MST TRX BB PIN AL AAS AD0 LRB
I C status register (S1)
F816
0
0
0
0
0
1
1
0
0
1
0
0
?
0
10 BIT
SAD
FAST
2
BSEL1 BSEL0
ALS ES0 BC2 BC1 BC0
CCR4 CCR3 CCR2 CCR1 CCR0
CM2
0016
0016
I C control register (S1D)
F916
FA16
FB16
FC16
FD16
FE16
FF16
ACK
ACK
2
I C clock control register (S2)
BIT
MODE
CM7 CM6 CM5
1
0
1
0
1
1
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
ADR VSCRCRTRTM4RTM3R TM2RTM1R
0016
T56R IICR INT2R 1MSR SIOR DSR INT1R
CK0
0016
0016
0016
0
ADE VSCECRTETM4E TM3E TM2E TM1E
INT2E1MSE SIOE DSE INT1E
T56ST56E IICE
Fig. 6. Memory Map of Special Function Register 1 (SFR2) (2)
13