MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR1 area (addresses C016 to DF16
)
<
Bit allocation
>
<
State immediately after reset >
:
: “0” immediately after reset
0
1
?
Function bit
:
:
Name
: “1” immediately after reset
No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
Address
b7
b0 b7
b0
Port P0 (P0)
C016
C116
C216
C316
?
0016
?
0016
?
0016
?
0016
?
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
C416
C516
C616
Port P2 direction register (D2)
Port P3 (P3)
Port P3 direction register (D3)
T3SC
P6IM
C716
C816
C916
CA16
CB16
CC16
Port P4 (P4)
Port P4 direction register (D4)
Port P5 (P5)
P46D P45D
0
0
0016
?
0016
OSD port control register (PF)
Port P6 (P6)
B
G
R
0
OUT2 OUT1
0
?
Port P7 (P7)
CD16
CE16
CF16
D016
0
0
0
0
0
?
?
?
OSD control register (OC)
Horizontal position register (HP)
OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0
HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0
0016
0016
?
Block control register 1 (BC )
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1
BC 0
1
1
1
1
1
1
1
1
1
Block control register 2 (BC )
D116
D216
D316
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1
BC 0
2 2 2 2 2 2 2
2
?
?
?
2
Block control register 3 (BC )
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1 BC 0
3
3
3
3
3
3
3
3
3
Block control register 4 (BC )
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1 BC 0
4
4
4
4
4
4
4
4
4
D416 Block control register 5 (BC )
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1
BC 0
5
?
5
5
5
5
5
5
5
5
D516 Block control register 6 (BC )
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1
BC 0
6
?
6
6
6
6
6
6
6
6
D616
D716
D816
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1 BC 0
7 7 7 7 7 7 7 7
Block control register 7 (BC )
?
7
Block control register 8 (BC )
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1 BC 0
?
?
8
8
8
8
8
8
8
8
8
BC 7 BC 6 BC 5 BC 4 BC 3 BC 2 BC 1
BC 0
9
Block control register 9 (BC )
9
9
9
10
11
12
13
14
15
9
9
9
9
9
BC
BC
BC
BC
BC
BC
BC
0
BC 7 BC
10
6
6
6
BC
BC
BC
5
5
5
5
5
5
BC 4 BC
10
3
3
3
3
3
3
BC
BC
BC
BC
BC
BC
BC
2
2
2
2
2
2
BC
BC
BC
BC
BC
BC
BC
1
1
1
1
1
1
Block control register 10 (BC
)
)
)
)
)
)
)
D916
10
11
12
13
14
15
16
10
11
12
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
?
?
?
?
10
11
12
13
14
15
16
0
0
0
0
0
0
BC 7 BC
11
BC 4 BC
11
DA16 Block control register 11 (BC
BC 7 BC
12
BC 4 BC
12
DB16
DC16
DD16
Block control register 12 (BC
Block control register 13 (BC
Block control register 14 (BC
BC 7 BC 6 BC
13 13
BC 4 BC
13
BC 7 BC 6 BC
BC 4 BC
14
14
14
?
?
?
DE16 Block control register 15 (BC
Block control register 16 (BC
BC 7 BC
15
6
BC
BC
BC 4 BC
15
15
DF16
2
1
16
BC
7
5
BC
4
BC
16
BC
6
3
16
16
16
16
16
Fig. 5. Memory Map of Special Function Register 1 (SFR1) (1)
12