MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ SFR2 area (addresses 22016 to 24816)
<Bit allocation>
<State immediately after reset >
:
:
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
: No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Address
Register
Bit allocation
State immediately after reset
b7
b0 b7
b0
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
0
0
0
0
0
0
0
0
0
22016
22116
22216
22316
?
?
?
?
?
?
?
?
?
1
1
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
2
2
2
2
2
2
2
2
2
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
3 3 3 3 3 3 3
3
3
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
4
4
4
4
4
4
4
4
4
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
Vertical position register 1 (VP1 )
22416
22516
22616
5
5
5
5
5
5
5
5
5
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
6
6
6
6
6
6
6
6
6
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
7
7
7
7
7
7
7
7
7
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
Vertical position register 1 (VP1 )
22716
22816
22916
22A16
22B16
22C16
8
8
8
8
8
8
8
8
8
Vertical position register 1 (VP1 )
VP1 7VP1 6 VP1 5 VP1 4VP1 3 VP1 2 VP1 1 VP1
9
9
9
9
9
9
9
9
9
Vertical position register 1 (VP1
10
)
)
)
VP1107VP1106VP1105 VP1104VP1103 VP1102 VP1101 VP110
0
?
?
?
?
10
11
12
VP1117VP1116VP1115 VP1114VP1113 VP1112 VP1111 VP1110
Vertical position register 1 (VP1
11
Vertical position register 1 (VP1
12
VP1127VP1126VP1125 VP1124VP1123 VP1122 VP1121 VP112
VP1137VP1136VP1135 VP1134VP1133 VP1132 VP1131 VP113
VP1147VP1146VP1145 VP1144VP1143 VP1142 VP1141 VP114
0
0
0
Vertical position register 1
(VP1
)
)
13
13
14
Vertical position register 1 (VP1
22D16
?
?
?
?
?
?
?
?
?
?
?
?
14
VP1157VP1156VP1155 VP1154VP1153 VP1152 VP1151 VP1150
VP1167VP1166VP1165 VP1164VP1163 VP1162 VP1161 VP116
22E16 Vertical position register 1 (VP1
15
22F16 Vertical position register 1 (VP1
16
)
)
15
16
0
VP21
VP22
VP23
VP24
VP25
VP26
1
1
1
1
1
1
VP210
Vertical position register 2 (VP2 )
23016
1
1
VP22
0
0
Vertical position register 2 (VP2 )
23116
23216
2
2
VP23
Vertical position register 2 (VP2 )
3
3
VP24
VP25
VP26
VP27
VP28
VP29
0
0
0
0
0
0
23316 Vertical position register 2 (VP2 )
4
4
23416
Vertical position register 2 (VP2 )
5
5
23516 Vertical position register 2 (VP2 )
6
6
VP27
VP28
VP29
1
Vertical position register 2 (VP2 )
23616
23716
23816
7
7
1
1
Vertical position register 2 (VP2 )
8
8
Vertical position register 2 (VP2 )
9
9
VP2101 VP210
VP2111 VP211
VP2121 VP212
0
0
0
?
?
?
?
Vertical position register 2 (VP2
)
23916
10
10
23A16 Vertical position register 2 (VP2
)
)
11
11
12
Vertical position register 2 (VP2
23B16
23C16
12
VP2131 VP213
0
Vertical position register 2 (VP2
13
)
)
13
14
VP2141 VP2140
VP2151 VP2150
VP2161 VP2160
?
?
?
?
23D16 Vertical position register 2 (VP2
14
23E16
23F16
24016
Vertical position register 2 (VP2
15
Vertical position register 2 (VP2
16
)
)
15
16
DA-H register (DA-H)
DA-L register (DA-L)
0
0
?
?
?
?
?
?
24116
0016
0016
0016
0016
0016
0016
0016
24216 ROM correction address 1 (high-order)
24316 ROM correction address 1 (low-order)
24416
ROM correction address 2 (high-order)
24516 ROM correction address 2 (low-order)
RCR1 RCR0
0
0016
0
ROM correction enable register (RCR)
24616
24716
24816
0
0
0
Fig. 8. Memory Map of Special Function Register 2 (SFR2) (2)
15
RENESAS [ RENESAS TECHNOLOGY CORP ]
