MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The M37274EFSP uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instruc-
tions or the SERIES 740 <Software> User’s Manual for details on
the instruction set.
CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1
0 0
CPU mode register (CPUM) (CM) [Address FB16
]
B
Name
Functions
After reset R W
Processor mode bits
(CM0, CM1)
b1 b0
0, 1
0
R W
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
3, 4 Fix these bits to “1.”
1
1
R W
R W
0: LOW drive
1: HIGH drive
X
COUT drivability
5
6
selection bit (CM5)
Main Clock (XIN–XOUT
stop bit
)
R W
R W
0
0
0: Oscillating
1: Stopped
(CM6)
Internal system clock
selection bit
(CM7)
7
0: XIN–XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(high-speed mode)
Note: This bit is set to “1” after the reset release.
Fig. 3. CPU Mode Register
10
RENESAS [ RENESAS TECHNOLOGY CORP ]
