M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8. FUNCTION BLOCK DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
8.1.1 CPU Mode Register
The CPU mode register includes a stack page selection bit and inter-
nal system clock selection bit. The CPU mode register is allocated to
address 00FB16.
Availability of 740 Family instructions is as follows:
The FST and SLW instructions cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1 1 1 1
0 0
CPU mode register (CM) [Address 00FB16
]
B
Name
Functions
After reset R W
Indeterminate
0, 1 Fix these bits to “0.”
R W
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
R W
Indeterminate
Fix these bits to “1.”
3 to 7
Note: This bit is set to “1” after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev.1.00 Oct 01, 2002 page 12 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
