M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Table 7.2 Pin Description (continued)
Output port P5
OSD output
Output
Output
Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
P52/R,
P53/G,
P54/B,
P55/OUT1
Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output
structure is CMOS output.
HSYNC input
VSYNC input
DA output
Input
Input
This is a horizontal synchronizing signal input for OSD.
This is a vertical synchronizing signal input for OSD.
This is a 14-bit PWM output pin.
HSYNC
VSYNC
D-A
Output
Note 1 : Port Pi (i = 0 to 3) has a port Pi direction register that can be used to program each bit for input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data is written into the port latch and then output. When data is read from the output pins, the
data of the port latch, not the output pin level, is read. This allows a previously output value to be read correctly even if the output LOW
voltage has risen due to, for example, a directly-driven light emitting diode. The input pins are in the floating state, so the values of the
pins can be read. When data is written to the input pin, it is written only into the port latch, while the pin remains in the floating state.
2 : To swich output structures, set by the following bits.
P30 : bit 0 of port P3 output mode control register
P31 : bit 1 of port P3 output mode control register
When “0,” CMOS output; when “1,” N-channel open-drain output.
3: Only M37221EASP/FP have a built-in D-A converter.
Rev.1.00 Oct 01, 2002 page 9 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
