455A Group
W51, W50
00
XCIN
01
ORCLK
Timer3 (16)
1 - - 4 - - - - - 9 10 11 12 13 14 15 16
10
11
Low-speed OCO
W32、W31、W30
High-speed OCO
111
W33
110
101
100
Timer 3
interrupt
T3F
011
Timer 3 underflow signal
(T3UDF)
010
001
000
W42
0
Timer LC (4)
1/2
LCD clock
1
STCK
W43
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
INSTCK
(Note 1)
S
Q
WDF1
R
WRST
instruction
Reset signal
(Note 3)
S
Q
WEF
Watchdog reset
signal
D
T
Q
R
DWDT instruction
+
WRST instruction
R
(Note 2)
reset signal
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
3: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig 34. Timers structure (2)
Rev.1.01 Feb 15, 2008 Page 33 of 146
REJ03B0224-0101
RENESAS [ RENESAS TECHNOLOGY CORP ]
