MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)
(1) Outline of TOP single-shot output mode
In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once
and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload
register, the counter is loaded with the content of the reload register and starts counting synchronously with
the count clock. The counter counts down and stops when it underflows after reaching the minimum count.
The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high or
vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload regis-
ter set value + 1) only once. An interrupt request can be generated when the counter underflows. The count
value is (reload register set value + 1).
For example, if the initial reload register value is 7, then the count value is 8.
Count value = 8
1
2
3
4
5
6
7
8
Count clock
Enable
H'FFFF
(Note 1)
(7)
6
Counter
5
4
3
2
1
0
Reload
register
7
F/F output
Interrupt request
* A count clock dependent delay is included before
F/F output changes state after the timer is enabled.
Underflow
Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7.
Note: • This diagram does not show detailed timing information.
Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode
32180 Group User’s Manual (Rev.1.0)
10-80
RENESAS [ RENESAS TECHNOLOGY CORP ]
