MULTIJUNCTION TIMERS
10.3 TOP (Output-Related 16-Bit Timer)
10
TOP Count Enable Register (TOPCEN)
<Address: H’0080 02FE>
b0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
TOP10
CEN
TOP9
CEN
TOP8
CEN
TOP7
CEN
TOP6
CEN
TOP5
CEN
TOP4
CEN
TOP3
CEN
TOP2
CEN
TOP1
CEN
TOP0
CEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<After reset: H’0000>
b
Bit Name
Function
R
0
W
0
0–4
5
No function assigned. Fix to "0".
TOP10CEN (TOP10 count enable bit)
TOP9CEN (TOP9 count enable bit)
TOP8CEN (TOP8 count enable bit)
TOP7CEN (TOP7 count enable bit)
TOP6CEN (TOP6 count enable bit)
TOP5CEN (TOP5 count enable bit)
TOP4CEN (TOP4 count enable bit)
TOP3CEN (TOP3 count enable bit)
TOP2CEN (TOP2 count enable bit)
TOP1CEN (TOP1 count enable bit)
TOP0CEN (TOP0 count enable bit)
0: Stop counting
R
W
6
1: Enable counting
7
8
9
10
11
12
13
14
15
Note: • This register must always be accessed in halfwords.
The TOP Count Enable Register controls operation of TOP counters. To enable any TOP counter in software,
enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TOP
counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0".
In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable
bit is automatically reset to "0". Therefore, the TOP0-10 Count Enable Register when accessed for read serves
as a status register indicating whether the counter is operating or idle.
TOPm external enable
(TOPmEEN)
F/F
Input processing
selection
EN-ON
TINnS
Event bus
TINn
TOPm count enable
(TOPmCEN)
Dn
TOP enable control
F/F
TOPm enable protect
(TOPmPRO)
WR
F/F
WR
Figure 10.3.6 Configuration of the TOP Enable Circuit
32180 Group User’s Manual (Rev.1.0)
10-79
RENESAS [ RENESAS TECHNOLOGY CORP ]
