DMAC
9.2 DMAC Related Registers
9
DMA2 Channel Control Register 0 (DM2CNT0)
<Address: H’0080 0430>
b0
1
2
0
3
0
4
5
6
b7
MDSEL2 TREQF2
REQSL2
TENL2 TSZSL2 SADSL2 DADSL2
0
0
0
0
0
0
<After reset: H’00>
b
0
Bit Name
MDSEL2
Function
R
R
W
W
0: Normal mode
DMA2 transfer mode select bit
1: Ring buffer mode
1
TREQF2
0: Transfer not requested
1: Transfer requested
R(Note 1)
DMA2 transfer request flag bit
2, 3
REQSL2
00: Software start
R
W
DMA2 transfer request source select bit
01: MJT (output event bus 1)
10: MJT (TIN18S)
11: Extended DMA2 transfer request source select
(DMA2 Channel Control Register 1)
4
5
6
7
TENL2
0: Disable transfer
1: Enable transfer
R
R
R
R
W
W
W
W
DMA2 transfer enable bit
TSZSL2
0: 16 bits
1: 8 bits
DMA2 transfer size select bit
SADSL2
0: Fixed
DMA2 source address direction select bit
1: Increment
DADSL2
0: Fixed
DMA2 destination address direction select bit
1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA2 Channel Control Register 1 (DM2CNT1)
<Address: H’0080 0431>
b8
0
9
0
10
0
11
0
12
0
13
14
b15
0
REQESEL2
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
W
0
8–11
No function assigned. Fix to "0".
REQESEL2
12–15
0000: One DMA1 transfer completed
0001: MJT(TID2_udf/ovf)
R
W
Extended DMA1 transfer request source select bit
0010: CAN(CAN0_S1/S14)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
|
|
1111: Settings inhibited
32180 Group User’s Manual (Rev.1.0)
9-8
RENESAS [ RENESAS TECHNOLOGY CORP ]
