DMAC
9.2 DMAC Related Registers
9
9.2.1 DMA Channel Control Registers
DMA0 Channel Control Register 0 (DM0CNT0)
<Address: H’0080 0410>
b0
1
2
3
4
5
6
b7
SADSL0 DADSL0
TENL0 TSZSL0
MDSEL0 TREQF0
REQSL0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
0
Bit Name
MDSEL0
Function
R
R
W
W
0: Normal mode
DMA0 transfer mode select bit
1: Ring buffer mode
1
TREQF0
0: Transfer not requested
1: Transfer requested
R(Note 1)
DMA0 transfer request flag bit
2, 3
REQSL0
00: Software start or one DMA2 transfer completed
01: A-D0 conversion completed
R
W
DMA0 transfer request source select bit
10: MJT (TIO8_udf)
11: Extended DMA0 transfer request source select
(DMA0 Channel Control Register 1)
4
5
6
7
TENL0
0: Disable transfer
1: Enable transfer
R
R
R
R
W
W
W
W
DMA0 transfer enable bit
TSZSL0
0: 16 bits
1: 8 bits
DMA0 transfer size select bit
SADSL0
0: Fixed
DMA0 source address direction select bit
1: Increment
DADSL0
0: Fixed
DMA0 destination address direction select bit
1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA0 Channel Control Register 1 (DM0CNT1)
<Address: H’0080 0411>
b8
9
10
11
12
13
14
b15
REQESEL0
0
0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
W
0
8–11
No function assigned. Fix to "0".
REQESEL0
12–15
0000: MJT (input event bus 2)
R
W
Extended DMA0 transfer request source select bit
0001: MJT (TID0_udf/ovf)
0010: CAN (CAN0_S0/S15)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
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1111: Settings inhibited
32180 Group User’s Manual (Rev.1.0)
9-6