DMAC
9.2 DMAC Related Registers
9
DMA5 Channel Control Register 0 (DM5CNT0)
<Address: H’0080 0418>
b0
1
2
0
3
0
4
5
6
b7
MDSEL5 TREQF5
REQSL5
TENL5 TSZSL5 SADSL5 DADSL5
0
0
0
0
0
0
<After reset: H’00>
b
0
Bit Name
MDSEL5
Function
R
R
W
W
0: Normal mode
DMA5 transfer mode select bit
1: Ring buffer mode
1
TREQF5
0: Transfer not requested
1: Transfer requested
R(Note 1)
DMA5 transfer request flag bit
2, 3
REQSL5
00: Software start or one DMA7 transfer completed
01: All DMA0 transfers completed
R
W
DMA5 transfer request source select bit
10: SIO2_RXD
11: Extended DMA5 transfer request source select
(DMA5 Channel Control Register 1)
4
5
6
7
TENL5
0: Disable transfer
1: Enable transfer
R
R
R
R
W
W
W
W
DMA5 transfer enable bit
TSZSL5
0: 16 bits
1: 8 bits
DMA5 transfer size select bit
SADSL5
0: Fixed
DMA5 source address direction select bit
1: Increment
DADSL5
0: Fixed
DMA5 destination address direction select bit
1: Increment
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA5 Channel Control Register 1 (DM5CNT1)
<Address: H’0080 0419>
b8
0
9
0
10
0
11
0
12
0
13
14
b15
0
REQESEL5
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
W
0
8–11
No function assigned. Fix to "0".
REQESEL5
12–15
0000: MJT(TIN20S)
R
W
Extended DMA5 transfer request source select bit
0001: MJT(TOU0_0irq)
0010: MJT(TOU2_7irq)
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
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1111: Settings inhibited
32180 Group User’s Manual (Rev.1.0)
9-11