INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
5
b0
1
9
2
3
11
4
5
6
14
b7
(b8
10
12
13
b15)
IREQ
0
ILEVEL
1
0
0
0
0
1
1
<After reset: H’07>
b
Bit Name
Function
R
0
W
0
0–2
No function assigned. Fix to "0"
(8–10)
3
IREQ
<When edge recognized>
At read
R
W
(11)
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
At write
0: Clear interrupt request
1: Generate interrupt request
<When level-recognized>
At read
R
0
0: Interrupt not requested
1: Interrupt requested
4
No function assigned. Fix to "0"
ILEVEL
0
0
(12)
5–7
000: Interrupt priority level 0
001: Interrupt priority level 1
010: Interrupt priority level 2
011: Interrupt priority level 3
100: Interrupt priority level 4
101: Interrupt priority level 5
110: Interrupt priority level 6
111: Interrupt priority level 7 (interrupt disabled)
R
W
(13–15) Interrupt priority level bits
(1) IREQ (Interrupt Request) bit (Bit 3 or 11)
When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Re-
quest) bit is set to "1".
This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for
level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re-
quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not
cleared in the case of level-recognized interrupt request).
If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in
software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the
same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority.
Note: • External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External
Interrupt (EI) to the CPU core can only be deasserted by the following operation:
(1) Reset
(2) IVECT register read
(3) Write to the IMASK register
32180 Group User’s Manual (Rev.1.0)
5-9