M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR
information.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
Register
Symbol
After Reset
(2)
00000000b(CNVSS pin is “L”)
00000011b(CNVSS pin is “H”)
Processor Mode Register 0
PM0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
00h
(6)
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
(6)
Data Bank Register
(3)
Oscillation Stop Detection Register
0X000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
RMAD0
XXh
00XXXXXXb
00h
00h
X0h
(4)
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
(5, 6)
Voltage Detection Register 1
Voltage Detection Register 2
Chip Select Expansion Control Register
PLL Control Register 0
VCR1
VCR2
CSE
00001000b
00h
00h
(5, 6)
(6)
PLC0
0001X010b
Processor Mode Register 2
Low Voltage Detection Interrupt Register
DMA0 Source Pointer
PM2
D4INT
SAR0
XXX00000b
00h
XXh
XXh
XXh
(6)
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DMA1 Source Pointer
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
DAR0
XXh
XXh
XXh
TCR0
XXh
XXh
DM0CON
SAR1
00000X00b
XXh
XXh
XXh
DAR1
XXh
XXh
XXh
TCR1
XXh
XXh
DM1CON
00000X00b
NOTES:
1.
2.
3.
4.
5.
6.
The blank areas are reserved and cannot be accessed by users.
The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program.
This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
This register in M16C/62PT cannot be used.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 34 of 96
REJ03B0001-0241
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