M16C/62P Group (M16C/62P, M16C/62PT)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H
R1H
R0L
R1L
Data Registers (1)
R2
R3
A0
A1
FB
Address Registers (1)
Frame Base Registers (1)
b19
b15
b0
Interrupt Table Register
Program Counter
INTBH
INTBL
b19
b0
b0
PC
b15
USP
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b15
b0
b0
FLG
O B
Flag Register
b15
b8 b7
IPL
U
I
S
Z
D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Rev.2.41 Jan 10, 2006 Page 30 of 96
REJ03B0001-0241
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