M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
(1)
Table 4.5
SFR Information (5)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
Count Start Flag
00h
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
0XXXXXXXb
00h
00h
00h
(2)
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
Timer B0 Register
Timer B1 Register
Timer B2 Register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
U0MR
U0BRG
U0TB
00h
XXh
XXh
XXh
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00XX0010b
XXh
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
00001000b
00XX0010b
XXh
XXh
UART Transmit/Receive Control Register 2
UCON
X0000000b
DMA0 Request Factor Select Register
DMA1 Request Factor Select Register
CRC Data Register
DM0SL
DM1SL
CRCD
00h
00h
XXh
XXh
XXh
CRC Input Register
CRCIN
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 38 of 96
REJ03B0001-0241
RENESAS [ RENESAS TECHNOLOGY CORP ]
