M16C/62 Group (M16C/62P, M16C/62PT)
4. SFR
4. SFR
Address
Register
Symbol
PM0
After reset
0000h
0001h
0002h
0003h
Processor mode register 0 (2)
00000000b(CNVSS pin is “L”)
0004h
00000011b(CNVSS pin is “H”)
Processor mode register 1
System clock control register 0
PM1
CM0
CM1
CSR
AIER
PRCR
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
0005h
0006h
System clock control register 1
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
Chip select control register (6)
Address match interrupt enable register
Protect register
Data bank register (6)
DBR
CM2
00h
0000X000b
Oscillation stop detection register (3)
Watchdog timer start register
WDTS
XXh
00XXXXXXb (4)
00h
00h
X0h
Watchdog timer control register
Address match interrupt register 0
WDC
RMAD0
Address match interrupt register 1
RMAD1
00h
00h
X0h
Voltage detection register 1 (5, 6)
VCR1
VCR2
CSE
00001000b
00h
00h
001Ah Voltage detection register 2 (5, 6)
001Bh
001Ch
001Dh
001Eh
Chip select expansion control register (6)
PLL control register 0
PLC0
0001X010b
Processor mode register 2
PM2
D4INT
SAR0
XXX00000b
00h
XXh
XXh
XXh
Voltage down detection interrupt register (6)
001Fh
0020h
DMA0 source pointer
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
DAR0
XXh
XXh
XXh
TCR0
XXh
XXh
DM0CON
00000X00b
DMA1 source pointer
SAR1
DAR1
XXh
XXh
XXh
DMA1 destination pointer
XXh
XXh
XXh
DMA1 transfer counter
DMA1 control register
TCR1
XXh
XXh
DM1CON
00000X00b
NOTES :
1. The blank areas are reserved and cannot be accessed by users.
2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
4. The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage
at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enable
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. This register cannot be used by M16C/62PT.
X : Nothing is mapped to this bit
page 24
Rev.2.10 Nov. 07, 2003
of 84
RENESAS [ RENESAS TECHNOLOGY CORP ]
