; Execute erase-verify
EVR:
MOV.W
MOV.W
ADD.W
MOV.W
SUB.W
#RAMSTR, R2
#ERVADR, R3
; Starting transfer destination address (RAM)
;
; #RAMSTR + #ERVADR → R2
;
R3,
R2
R3
R2
#START,
R3,
; Address of data area used in RAM
MOV.B
MOV.B
BSET
#H'00,
#H'b,
#3,
R1L
R4H
@FLMCR:8
; Used to test R1L bit in R0
; Set erase-verify loop counter
;
Set EV bit
LOOPEV: DEC
R4H
;
BNE
LOOPEV
#H'0C,
HANTEI
#H'08,
EBR2EV
R1L,
#H'08,
R1H,
ERSEVF
ADD01
R1L,
; Wait loop
; R1L = H'0C?
; If finished checking all R0 bits, branch to HANTEI
;
; Test EBR1 if R1L ≥ 8, or EBR2 if R1L < 8
;
; R1L – 8 → R1H
; Test R1H bit in EBR1 (R0H)
; If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF
; If R1H bit in EBR1 (R0H) is 0, branch to ADD01
; Test R1L bit in EBR2 (R0L)
; If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF
; R1L + 1 → R1L
EBRTST: CMP.B
R1L
R1L
BEQ
CMP.B
BMI
MOV.B
SUBX
BTST
BNE
BRA
R1H
R1H
R0H
EBR2EV: BTST
BNE
R0L
R3
ERSEVF
R1L
@R2+,
EBRTST
ADD01:
INC
MOV.W
BRA
; Dummy-increment R2
;
ERASE1: BRA
ERASE
; Branch to ERASE via Erase 1
ERSEVF: MOV.W
@R2+,
#H'FF,
R1H,
#H'c,
R4H
LOOPEP
@R3+,
#H'FF,
BLKAD
@R2,
R3
; Top address of block to be erase-verified
;
; Dummy write
; Set erase-verify loop counter
;
; Wait loop
; Read
; Read data = H'FF?
; If read data ≠ H'FF branch to BLKAD
; Top address of next block
; Last address of block?
EVR2:
MOV.B
MOV.B
MOV.B
R1H
@R3
R4H
LOOPEP: DEC
BNE
MOV.B
CMP.B
BNE
MOV.W
CMP.W
BNE
R1H
R1H
R4
R3
R4,
EVR2
CMP.B
BMI
MOV.B
SUBX
BCLR
BRA
#H'08,
SBCLR
R1L,
#H'08,
R1H,
BLKAD
R1L,
R1L
R1L
; Test EBR1 if R1L ≥ 8, or EBR2 if R1L < 8
;
; R1L – 8 → R1H
; Clear R1H bit in EBR1 (R0H)
R1H
R1H
R0H
SBCLR:
BLKAD:
BCLR
INC
R0L
; Clear R1L bit in EBR2 (R0L)
; R1L + 1 → R1L
BRA
EBRTST
;
HANTEI: BCLR
MOV.W
#3,
R0,
EOWARI
@FLMCR:8
@EBR1
;
Clear EV bit
;
BEQ
; If EBR1/EBR2 is all 0, erasing ended normally
406
RENESAS [ RENESAS TECHNOLOGY CORP ]
