Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to the on-
chip supporting modules. For details, see section 6, Clock Pulse Generator.
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0)
Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0)
These bits control insertion of wait states by the wait-state controller. For details, see section 5,
Wait-State Controller.
Notes: *1 For details on emulation protect, see section 19.4.8, Protect Modes.
*2 For details on interrupt handling during programming and erasing of flash memory, see
section 19.4.9, Interrupt Handling during Flash Memory Programming and Erasing.
*3 RAM area that overlaps flash memory.
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