Output Timing: When a compare-match event occurs, the timer output changes as specified by
the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain
the same, change to 0, change to 1, or toggle.
Figure 9.5 shows the timing when the output is set to toggle on compare-match A.
ø
Internal compare-
match A signal
Timer output
(TMO)
Figure 9.5 Timing of Timer Output
Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the timer
counter can be cleared when compare-match A or B occurs. Figure 9.6 shows the timing of this
operation.
ø
Internal compare-
match signal
TCNT
N
H'00
Figure 9.6 Timing of Compare-Match Clear
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RENESAS [ RENESAS TECHNOLOGY CORP ]
