9.6.2
Contention between TCNT Write and Increment
If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer
counter, the write takes priority and the timer counter is not incremented.
Figure 9.11 shows this type of contention.
Write cycle: CPU writes to TCNT
T1
T2
T3
ø
Internal address bus
TCNT address
Internal write signal
TCNT clock pulse
TNCT
N
M
Write data
Figure 9.11 TCNT Write-Increment Contention
208