Section 17 I2C Bus Interface 2 (IIC2)
Initial
Bit
Bit Name Value
R/W
Description
6
TEIE
0
R/W
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit in
ICSR is 1. TEI can be canceled by clearing the TEND bit
or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Receive Interrupt Enable
5
RIE
0
R/W
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request
(ERI) with the clock synchronous format, when a receive
data is transferred from ICDRS to ICDRR and the RDRF
bit in ICSR is set to 1. RXI can be canceled by clearing
the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clock
synchronous format are disabled.
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clock
synchronous format are enabled.
4
NAKIE
0
R/W
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the OVE
bit in ICSR) interrupt request (ERI) with the clock
synchronous format, when the NACKF and AL bits in
ICSR are set to 1. NAKI can be canceled by clearing the
NACKF, OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
Stop Condition Detection Interrupt Enable
3
STIE
0
R/W
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
Rev. 3.00 Sep. 10, 2007 Page 339 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
