Section 14 Watchdog Timer
14.2.2
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.
14.2.3
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Initial
Bit
Bit Name Value
R/W
Description
7 to 4
All 1
Reserved
These bits are always read as 1.
Clock Select 3 to 0
3
2
1
0
CKS3
CKS2
CKS1
CKS0
1
1
1
1
R/W
R/W
R/W
R/W
Select the clock to be input to TCWD.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
0XXX: WDT dedicated internal oscillator
For the overflow periods of the WDT dedicated internal
oscillator, see section 22, Electrical Characteristics.
[Legend]X: Don't care.
Rev. 3.00 Sep. 10, 2007 Page 278 of 528
REJ09B0216-0300
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