Section 14 Watchdog Timer
14.3
Operation
The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD
starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is
generated. The internal reset signal is output for a period of 256 φOSC clock cycles. As TCWD is a
writable counter, it starts counting from the value set in TCWD. An overflow period in the range
of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. When the
watchdog timer is not used, stop TCWD counting by writing 0 to B2WI and WDON
simultaneously while the TCSRWE bit in TCSRWD is set to 1. (To stop the watchdog timer, two
write accesses to TCSRWD are required.)
Figure 14.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when φ = 4 MHz
4 × 106
8192
× 30 × 10–3 = 14.6
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
H'F1 written H'F1 written to TCWD
to TCWD
Reset generated
Internal reset
signal
256 φOSC clock cycles
Figure 14.2 Watchdog Timer Operation Example
Rev. 3.00 Sep. 10, 2007 Page 279 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
