Section 13 Timer Z
Reset synchronous PWM mode
[1] Clear bit STR0 in TSTR to 0 and stop the
counter operation of TCNT_0. Set reset
synchronous PWM mode after TCNT_0
stops.
[1]
Stop counter operation
Select counter clock
[2] Select the counter clock with bits TPSC2
to TOSC0 in TCR. When an external
clock is selected, select the external clock
edge with bits CKEG1 and CKEG0 in
TCR.
[3] Use bits CCLR1 and CCLR0 in TCR to
select counter clearing source GRA_0.
[4] Select the reset synchronous PWM mode
with bits CMD1 and CMD0 in TFCR.
FTIOB0 to FTIOD0 and FTIOA1 to
FTIOD1 become PWM output pins
automatically.
[2]
[3]
Select counter clearing source
[4]
Set reset synchronous PWM mode
[5] Set H'00 to TOCR.
[6] Set TCNT_0 as H'0000. TCNT1 does not
need to be set.
[5]
[6]
[7]
[7] GRA_0 is a cycle register. Set a cycle for
GRA_0. Set the changing point timing of
the PWM output waveform for GRB_0,
GRA_1, and GRB_1.
[8] Enable or disable the timer output by
TOER.
Initialize the output pin
Set TCNT
[9] Set the STR bit in TSTR to 1 and start the
counter operation.
Set GR
[8]
[9]
Enable waveform output
Start counter operation
<Reset synchronous PWM mode>
Figure 13.26 Example of Reset Synchronous PWM Mode Setting Procedure
Rev. 3.00 Sep. 10, 2007 Page 241 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
