HD6417709SF133B 参数 Datasheet PDF下载

型号：	HD6417709SF133B
PDF下载：	下载PDF文件查看货源
内容描述：	瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用：	微控制器和处理器外围集成电路时钟
文件页数/大小：	807 页 / 4409 K
品牌：	RENESAS [ RENESAS TECHNOLOGY CORP ]

R0_BANK1^{*1 *2}

R1_BANK1^*2

R2_BANK1^*2

R3_BANK1^*2

R4_BANK1^*2

R5_BANK1^*2

R6_BANK1^*2

R7_BANK1^*2

R0_BANK0^{*1 *3}

R1_BANK0^*3

R2_BANK0^*3

R3_BANK0^*3

R4_BANK0^*3

R5_BANK0^*3

R6_BANK0^*3

R7_BANK0^*3

R10

R11

R12

R13

R14

R15

SSR

Notes:

1. R0 functions as an index

GBR

MACH

MACL

GBR

MACH

MACL

mode and indexed GBR-

indirect addressing mode.

2. Banked register

VBR

When the RB bit of the SR

be accessed for general use.

When the RB bit is 0, it can

only be accessed with the

LDC/STC instruction.

SPC

R0_BANK0^{*1 *3}

R1_BANK0^*3

R2_BANK0^*3

R3_BANK0^*3

R4_BANK0^*3

R5_BANK0^*3

R6_BANK0^*3

R7_BANK0^*3

R0_BANK1^{*1 *2}

R1_BANK1^*2

R2_BANK1^*2

R3_BANK1^*2

R4_BANK1^*2

R5_BANK1^*2

R6_BANK1^*2

R7_BANK1^*2

3. Banked register

When the RB bit of the SR

be accessed for general use.

When the RB bit is 1, it can

only be accessed with the

LDC/STC instruction.

a. Privileged mode

(RB = 1)

b. Privileged mode

(RB = 0)

Figure 2.2 Privileged Mode Register Configuration

Rev. 5.00, 09/03, page 21 of 760

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HD6417709SF133B 参数 Datasheet PDF下载

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