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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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8.4.2  
Canceling Standby Mode  
Standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or on-chip peripheral module)  
or a reset.  
Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects  
1
an NMI, IRL, IRQ, PINT , or on-chip peripheral module (except interval timer) 2 interrupt, the  
clock will be supplied to the entire chip and standby mode canceled after the time set in the  
WDT’s timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low.  
Interrupt handling then begins and a code indicating the interrupt source is set in the INTEVT and  
INTEVT2 registers. After the branch to the interrupt handling routine, clear the STBY bit in the  
STBCR register. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues  
*
*
operation and a transition is made to standby mode 3 when it reaches H'80. This function prevents  
*
the data from being destroyed due to a rise in voltage with an unstable power supply, etc.  
Interrupts are accepted in standby mode even when the BL bit in the SR register is 1. If necessary,  
save SPC and SSR to the stack before executing the SLEEP instruction. Immediately after an  
interrupt is detected, the phase of the CKIO pin clock output may be unstable, until the processor  
starts interrupt handling. (The canceling condition is that the IRL3–IRL0 level is higher than the  
mask level in the I3–I0 bits in the SR register.)  
Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3–IRL0, IRQ4–  
IRQ0, or PINT0/1.  
2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC  
clock) interrupt.  
3. This standby mode can be canceled only by a power-on reset.  
Interrupt  
request  
WDT overflow and branch to  
interrupt handling routine  
Crystal oscillator settling  
time and PLL synchronization  
time  
Clear bit STBCR.STBY before  
WTCNT reaches H'80. When  
STBCR.STBY is cleared, WTCNT  
halts automatically.  
WTCNT value  
H'FF  
H'80  
Time  
Figure 8.1 Canceling Standby Mode with STBCR.STBY  
Rev. 5.00, 09/03, page 189 of 760  
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