CKIO
tDBQS
tDBQH
DBREQ
tBAVD
tBAVD
BAVL
TR
tTRS
tTRH
tDTRS
tDTRH
D63 to D0
(READ)
(2)
(1)
(1): [2CKIO cycle – tDTRS] (= 18 ns: 100 MHz)
(2): DTR = 1CKIO cycle (= 10 ns: 100 MHz)
(tDTRS + tDTRH) < DTR < 10 ns
Figure 22.66(b) '%5(4/75 Input Timing and %$9/ Output Timing
tTCKcyc
tTCKL
tTCKH
VIH
VIH
VIH
1/2VDDQ
1/2VDDQ
VIL
VIL
tTCKf
tTCKr
Note: When clock is input from TCK pin
Figure 22.67 TCK Input Timing
(Low)
SCK2/
(High)
tASEBRKS tASEBRKH
tASEBRKS
tASEBRKH
/
BRKACK
Figure 22.68 5(6(7 Hold Timing
Rev. 6.0, 07/02, page 932 of 986