22.3.6 Delay Time Variation Due to Load Capacitance
A graph (reference data) of the variation in delay time when a load capacitance greater than that
stipulated (30 pF) is connected to the SH7750 Series’ pins is shown below. The graph shown in
figure 22.73 should be taken into consideration if the stipulated capacitance is exceeded when
connecting an external device.
The graph will not be linear if the connected load capacitance exceeds the range shown in figure
22.73.
+4.0 ns
+3.0 ns
+2.0 ns
+1.0 ns
+0.0 ns
+0 pF
+25 pF
Load Capacitance
+50 pF
Figure 22.73 Load Capacitance vs. Delay Time
Rev. 6.0, 07/02, page 935 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
