Table 22.36 Peripheral Module Signal Timing (3)
HD6417750
F167
HD6417750
VF128
HD6417750
F167I
HD6417750
BP200M
2
3
4
*
*
*
Module Item
Symbol Min
Max
Min
Max
Min
Max Unit
Figure
1
1
*
*
TMU,
RTC
Timer clock
pulse width
(high)
tTCLKWH
4
—
4
—
4
—
Pcyc
22.61
Timer clock
pulse width
(low)
tTCLKWL
4
—
4
—
4
—
Pcyc
22.61
1
1
*
*
Timer clock
rise time
tTCLKr
tTCLKf
tROSC
tScyc
—
—
—
4
0.8
0.8
3
—
—
—
4
0.8
0.8
3
—
—
—
4
0.8
0.8
3
Pcyc
Pcyc
s
22.61
22.61
22.62
22.63
Timer clock
fall time
Oscillation
settling time
1
1
*
*
SCI
Input clock
cycle (asyn-
chronous)
—
—
—
Pcyc
Input clock
cycle (syn-
chronous)
tScyc
6
—
6
—
6
—
Pcyc
22.63
Input clock
pulse width
tSCKW
tSCKr
tSCKf
0.4
—
0.6
0.8
0.8
10
0.4
—
0.6
0.8
0.8
8
0.4
—
0.6
0.8
0.8
6
tScyc
22.63
22.63
22.63
22.64
22.64
1
1
*
*
Input clock
rise time
Pcyc
Pcyc
ns
Input clock
fall time
—
—
—
Transfer data tTXD
delay time
1.3
16
1.3
16
1.2
16
Receive data tRXS
setup time
—
—
—
ns
(synchronous)
Receive data tRXH
hold time
16
—
16
—
16
—
ns
22.64
(synchronous)
I/O
ports
Output data
delay time
tPORTD
0.5
3.5
1.5
10
—
—
0.5
3.5
1.5
8
0.5
3
6
ns
ns
ns
22.65
22.65
22.65
Input data
setup time
tPORTS
—
—
—
—
Input data
hold time
tPORTH
1.5
Rev. 6.0, 07/02, page 928 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
