HD6417750
F167
HD6417750
VF128
HD6417750
F167I
HD6417750
BP200M
2
3
4
*
*
*
Module Item
Symbol Min
Max
Min
Max
Min
Max Unit
Figure
DMAC
'5(4Q
tDRQS
tDRQH
tDRAKD
tNMIH
3.5
1.5
1.0
—
3.5
—
3
—
—
6
ns
ns
ns
22.66
setup time
'5(4Q
—
1.5
1.0
—
8
1.5
1.0
22.66
22.66
hold time
DRAKn
delay time
10
Normal or sleep mode
Standby mode
INTC
NMI pulse
width (high)
5
—
—
—
—
—
5
—
—
—
—
—
5
—
—
—
—
—
tcyc
ns
tcyc
ns
ns
22.71
22.71
22.71
22.71
22.67
30
5
30
5
30
5
Normal or sleep mode
Standby mode
NMI pulse
width (low)
tNMIL
30
50
30
50
30
50
H-UDI
Input clock
cycle
tTCKcyc
Input clock
pulse width
(high)
tTCKH
15
15
—
—
15
15
—
—
15
15
—
—
ns
ns
22.67
22.67
Input clock
pulse width
(low)
tTCKL
Input clock
rise time
tTCKr
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
ns
22.67
22.67
22.68
22.68
22.69
22.69
22.69
22.70
Input clock
fall time
tTCKf
ns
$6(%5.
tASEBRKS
tASEBRKH
tTDIS
tcyc
setup time
$6(%5.
tcyc
hold time
TDI/TMS
setup time
ns
TDI/TMS
hold time
tTDIH
ns
TDO delay
time
tTDO
ns
1
*
ASE-PINBRK tPINBRK
pulse width
2
2
2
Pcyc
Notes: *1 Pcyc: P clock cycles
*2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
*3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
(HD6417750F167)
V
DDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –40 to +85°C, CL = 30 pF, PLL2 on
(HD6417750F167I)
*4 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
Rev. 6.0, 07/02, page 929 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
