HD6417750
RBP240
HD6417750
RBP200
HD6417750
RF240
HD6417750
RF200
2
2
2
2
*
*
*
*
Module Item
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit
Figure
I/O
ports
Output data
delay time
tPORTD
tPORTS
tPORTH
tDRQS
tDRQH
tDRAKD
tNMIH
1.5
5.3
1.5
6
1.5
6
1.5
6
ns
ns
ns
ns
ns
ns
tcyc
22.65
Input data
setup time
2
—
—
—
—
5.3
—
2.5
1.5
2.5
1.5
1.5
5
—
—
—
—
6
3.5
1.5
3.5
1.5
1.5
5
—
—
—
—
6
3.5
1.5
3.5
1.5
1.5
5
—
—
—
—
6
22.65
22.65
22.66
22.66
22.66
22.71
Input data
hold time
1.5
2
DMAC
'5(4Q
setup time
'5(4Q
1.5
1.5
5
hold time
DRAKn
delay time
Normal
or sleep
mode
INTC
NMI pulse
—
—
—
width (high)
Standby
mode
30
5
—
—
30
5
—
—
30
5
—
—
30
5
—
—
ns
tcyc
22.71
22.71
Normal
or sleep
mode
NMI pulse
width (low)
tNMIL
Standby
mode
30
50
15
—
—
—
30
50
15
—
—
—
30
50
15
—
—
—
30
50
15
—
—
—
ns
ns
ns
22.71
22.67
22.67
H-UDI
Input clock
cycle
tTCKcyc
Input clock
pulse width
(high)
tTCKH
Input clock
pulse width
(low)
tTCKL
15
—
15
—
15
—
15
—
ns
22.67
Input clock
rise time
tTCKr
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
—
—
10
10
15
15
0
10
10
—
—
—
—
10
—
ns
22.67
22.67
22.68
22.68
22.69
22.69
22.69
22.70
Input clock
fall time
tTCKf
ns
tASEBRKS
tASEBRKH
tTDIS
tcyc
$6(%5.
setup time
$6(%5.
tcyc
hold time
TDI/TMS
setup time
ns
TDI/TMS
hold time
tTDIH
ns
TDO delay
time
tTDO
ns
1
*
ASE-PINBRK tPINBRK
pulse width
2
2
2
2
Pcyc
Notes: *1 Pcyc: P clock cycles
*2 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
Rev. 6.0, 07/02, page 925 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
