TS1
T1
T2
TH1
CKIO
tAD
tAD
A25–A0
tCSD
tCSD
tRWD
tRWD
RD/
tRSD
tRSD
tRSD
tRDS
tWEDF
tRDH
D63–D0
(read)
tWED1
tWED1
tBSD
tBSD
tDACD
tDACD
DACKn
(SA: IO ← memory)
tDACD
tDACD
DACKn
(DA)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address
Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1)
Rev. 6.0, 07/02, page 923 of 986