Table 20.1 shows the UBC registers.
Table 20.1 UBC Registers
Area 7
Access
Size
Name
Abbreviation R/W
Initial Value P4 Address Address
Break address
register A
BARA
R/W
Undefined
H'FF200000 H'1F200000 32
Break address
mask
BAMRA
R/W
Undefined
H'FF200004 H'1F200004
8
register A
Break bus
cycle register A
BBRA
R/W
R/W
R/W
R/W
H'0000
H'FF200008 H'1F200008 16
H'FF000014 H'1F000014
H'FF20000C H'1F20000C 32
H'FF200010 H'1F200010
Break ASID
register A
BASRA
BARB
Undefined
Undefined
Undefined
8
Break address
register B
Break address
mask
BAMRB
8
register B
Break bus
cycle register B
BBRB
R/W
R/W
R/W
R/W
R/W
H'0000
H'FF200014 H'1F200014 16
H'FF000018 H'1F000018
Break ASID
register B
BASRB
BDRB
Undefined
Undefined
Undefined
H'0000*
8
Break data
register B
H'FF200018 H'1F200018 32
H'FF20001C H'1F20001C 32
H'FF200020 H'1F200020 16
Break data
mask register B
BDMRB
BRCR
Break control
register
Note: * Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for
details.
Rev. 6.0, 07/02, page 775 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
