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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Start  
bit  
Data  
Parity Stop Start  
Data  
Parity Stop  
1
bit  
bit bit  
bit  
bit  
Serial  
data  
0
D0  
D1  
D7 0/1  
1
0
D0 D1  
D7 0/1  
0
0/1  
RDF  
FER  
RXI interrupt  
request  
Data read and RDF flag  
read as 1 then cleared to  
0 by RXI interrupt handler  
ERI interrupt request  
generated by receive  
error  
One frame  
Figure 16.11 Example of SCIF Receive Operation  
(Example with 8-Bit Data, Parity, One Stop Bit)  
5. When modem control is enabled, the 5765 signal is output when SCFRDR2 is empty. When  
5765 is 0, reception is possible.  
SH7750:  
When 5765 is 1, this indicates that SCFRDR2 contains 15 or more  
bytes of data.  
SH7750S, SH7750R: When 5765 is 1, this indicates that SCFRDR2 contains a number of  
data bytes equal to or greater than the 5765 output active trigger set  
number. The 5765 output active trigger value is specified by bits 10 to  
8 in the FIFO control register (SCFCR2), described in section 16.2.9,  
FIFO control register (SCFCR2).  
5765 also becomes 1 when bit 4 (RE) in SCSCR2 is 0.  
Figure 16.12 shows an example of the operation when modem control is used.  
Start  
bit  
Parity Stop  
Start  
bit  
bit  
bit  
Serial data  
RxD2  
0
D0 D1 D2  
D7 0/1  
1
0
Figure 16.12 Example of Operation Using Modem Control (5765)  
Rev. 6.0, 07/02, page 696 of 986  
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