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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号HD6417750SBP200的Datasheet PDF文件第742页浏览型号HD6417750SBP200的Datasheet PDF文件第743页浏览型号HD6417750SBP200的Datasheet PDF文件第744页浏览型号HD6417750SBP200的Datasheet PDF文件第745页浏览型号HD6417750SBP200的Datasheet PDF文件第747页浏览型号HD6417750SBP200的Datasheet PDF文件第748页浏览型号HD6417750SBP200的Datasheet PDF文件第749页浏览型号HD6417750SBP200的Datasheet PDF文件第750页  
1. Whether a framing error or parity error  
has occurred that is to be read from  
SCFRDR2 can be ascertained from  
the FER and PER bits in SCFSR2.  
Error handling  
ORER = 1?  
No  
No  
No  
2. When a break signal is received,  
receive data is not transferred to  
SCFRDR2 while the BRK flag is set.  
However, note that the last data in  
SCFRDR2 is H'00 (the break data in  
which a framing error occurred is  
stored).  
Yes  
Overrun error handling  
ER = 1?  
Yes  
Receive error handling  
BRK = 1?  
Yes  
Break handling  
No  
DR = 1?  
Yes  
Read receive data in SCFRDR2  
Clear DR, ER, BRK flags  
in SCFSR2,  
and ORER flag in SCLSR2, to 0  
End  
Figure 16.10 Sample Serial Reception Flowchart (2)  
Rev. 6.0, 07/02, page 694 of 986  
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