Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive
input pin (RxD2), and the 5765 pin and &765 pin, enabling loopback testing.
Bit 0: LOOP
Description
0
1
Loopback test disabled
Loopback test enabled
(Initial value)
16.2.10 FIFO Data Count Register (SCFDR2)
SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and
SCFRDR2.
The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show
the number of receive data bytes in SCFRDR2.
SCFDR2 can be read by the CPU at all times.
Bit:
15
—
0
14
—
0
13
—
0
12
T4
0
11
T3
0
10
T2
0
9
T1
0
8
T0
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates
that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data.
Bit:
7
—
0
6
—
0
5
—
0
4
R4
0
3
R3
0
2
R2
0
1
R1
0
0
R0
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that
there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data.
Rev. 6.0, 07/02, page 678 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
