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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during  
reception.*  
Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is  
cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2,  
and reception continues.  
The FER and PER bits in SCFSR2 can be used to determine whether there is a receive  
error that is to be from SCFRDR2.  
Bit 7: ER  
Description  
0
No framing error or parity error occurred during reception  
[Clearing conditions]  
(Initial value)  
Power-on reset or manual reset  
When 0 is written to ER after reading ER = 1  
1
A framing error or parity error occurred during reception  
[Setting conditions]  
When the SCIF checks whether the stop bit at the end of the receive  
data is 1 when reception ends, and the stop bit is 0*  
When, in reception, the number of 1-bits in the receive data plus the  
parity bit does not match the parity setting (even or odd) specified by the  
O/( bit in SCSMR2  
Note: * In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is  
not checked.  
Rev. 6.0, 07/02, page 669 of 986  
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