Tr1
Tr2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tce
Tpc
CKIO
r
c1
c2
c3
c4
A25–A0
RD/
D63–D0
(read)
d1
d2
d3
d4
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.21 Burst Access Timing in DRAM EDO Mode
RAS Down Mode: The SH7750 Series has an address comparator for detecting row address
matches in burst mode. By using this address comparator, and also setting RAS down mode
specification bit RASD to 1, it is possible to select RAS down mode, in which 5$6 remains
asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer
than the maximum DRAM 5$6 assert time, the refresh cycle must be decreased to or below the
maximum value of tRAS
.
RAS down mode can only be used when DRAM is connected in area 3.
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus request, 5$6 is negated and the necessary operation
is performed. When DRAM access is resumed after this, since this is the start of RAS down mode,
the operation starts with row address output. Timing charts are shown in figures 13.22 (1), (2), (3),
and (4).
Rev. 6.0, 07/02, page 404 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
