Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
:(6,
:(5,
:(4,
:(3,
Access
Size
&$66, &$65, &$64, &$63,
Address No. D31–D24 D23–D16 D15–D8 D7–D0
DQM3 DQM2 DQM1 DQM0
Byte
4n
1
1
1
1
1
1
1
1
2
—
—
Data
7–0
Asserted
4n+1
4n+2
4n+3
4n
—
—
—
Data
7–0
—
—
—
Asserted
Data
7–0
—
Asserted
Data
7–0
—
—
Asserted
Word
—
—
Data
15–8
Data
7–0
Asserted Asserted
4n+2
4n
Data
15–8
Data
7–0
—
—
Asserted Asserted
Long-
word
Data
31–24
Data
23–16
Data
15–8
Data
7–0
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Quad-
word
8n
Data
31–24
Data
23–16
Data
15–8
Data
7–0
8n+4
Data
Data
Data
Data
63–56
55–48
47–40
39–32
Rev. 6.0, 07/02, page 379 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
