Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
:(6,
:(5,
:(4,
:(3,
Access
Size
&$66,
DQM3
&$65,
&$64,
DQM1
&$63,
DQM0
Address No. D31–D24 D23–D16 D15–D8 D7–D0
DQM2
Byte
2n
1
1
1
1
2
1
2
3
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data
7–0
—
Asserted
2n+1
—
Data
7–0
Asserted
Word 2n
Data
15–8
Data
7–0
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Long- 4n
word
Data
31–24
Data
23–16
4n+2
Data
15–8
Data
7–0
Quad- 8n
word
Data
63–56
Data
55–48
8n+2
Data
47–40
Data
39–32
8n+4
8n+6
Data
31–24
Data
23–16
Data
15–8
Data
7–0
Rev. 6.0, 07/02, page 375 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
