Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
:(6,
&$66,
DQM3
:(5,
:(4,
&$64,
DQM1
:(3,
&$63,
DQM0
Access
Size
&$65,
Address No. D31–D24 D23–D16 D15–D8 D7–D0
DQM2
Byte
4n
1
1
1
1
1
1
1
1
2
Data
7–0
—
—
—
—
—
Asserted
4n+1
4n+2
4n+3
—
—
—
Data
7–0
—
Asserted
—
Data
7–0
Asserted
—
—
Data
7–0
Asserted
Word 4n
Data
15–8
Data
7–0
—
—
Asserted Asserted
4n+2
—
—
Data
15–8
Data
7–0
Asserted Asserted
Long- 4n
word
Data
Data
Data
15–8
Data
7–0
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
31–24
23–16
Quad- 8n
word
Data
Data
Data
Data
63–56
55–48
47–40
39–32
8n+4
Data
Data
Data
15–8
Data
7–0
31–24
23–16
Rev. 6.0, 07/02, page 374 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
