Round to Zero: The digits below the round bit of the unrounded value are discarded.
If the unrounded value is larger than the maximum expressible absolute value, the value will be
the maximum expressible absolute value.
6.5
Floating-Point Exceptions
FPU-related exceptions are as follows:
•
General illegal instruction/slot illegal instruction exception
The exception occurs if an FPU instruction is executed when SR.FD = 1.
•
FPU exceptions
The exception sources are as follows:
FPU error (E): When FPSCR.DN = 0 and a denormalized number is input
Invalid operation (V): In case of an invalid operation, such as NaN input
Division by zero (Z): Division with a zero divisor
Overflow (O): When the operation result overflows
Underflow (U): When the operation result underflows
Inexact exception (I): When overflow, underflow, or rounding occurs
The FPSCR cause field contains bits corresponding to all of above sources E, V, Z, O, U, and
I, and the FPSCR flag and enable fields contain bits corresponding to sources V, Z, O, U, and
I, but not E. Thus, FPU errors cannot be disabled.
When an exception source occurs, the corresponding bit in the cause field is set to 1, and 1 is
added to the corresponding bit in the flag field. When an exception source does not occur, the
corresponding bit in the cause field is cleared to 0, but the corresponding bit in the flag field
remains unchanged.
•
Enable/disable exception handling
The SH7750 Series supports enable exception handling and disable exception handling.
Enable exception handling is initiated in the following cases:
FPU error (E): FPSCR.DN = 0 and a denormalized number is input
Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)
Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor
Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result
overflow
Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result
underflow
Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation
result
Rev. 6.0, 07/02, page 169 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
