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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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If the accepted exception (the highest-priority exception) is a delay slot instruction re-  
execution type exception, the branch instruction PR register write operation (PC PR  
operation performed in BSR, BSRF, JSR) is inhibited.  
5.7  
Usage Notes  
1. Return from exception handling  
a. Check the BL bit in SR with software. If SPC and SSR have been saved to external  
memory, set the BL bit in SR to 1 before restoring them.  
b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR  
contents are set in SR, and branch is made to the SPC address to return from the exception  
handling routine.  
2. If an exception or interrupt occurs when SR.BL = 1  
a. Exception  
When an exception other than a user break occurs, a manual reset is executed. The value in  
EXPEVT at this time is H'0000 0020; the value of the SPC and SSR registers is undefined.  
b. Interrupt  
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after  
the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)  
occurs, it can be held pending or accepted according to the setting made by software. In the  
sleep or standby state, however, an interrupt is accepted even if the BL bit in SR is set to 1.  
3. SPC when an exception occurs  
a. Re-execution type exception  
The PC value for the instruction in which the exception occurred is set in SPC, and the  
instruction is re-executed after returning from exception handling. If an exception occurs in  
a delay slot instruction, however, the PC value for the delay slot instruction is saved in SPC  
regardless of whether or not the preceding delay slot instruction condition is satisfied.  
b. Completion type exception or interrupt  
The PC value for the instruction following that in which the exception occurred is set in  
SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value  
for the branch destination is saved in SPC.  
4. An exception must not be generated in an RTE instruction delay slot, as the operation will be  
undefined in this case.  
Rev. 6.0, 07/02, page 159 of 986  
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