(11) General FPU Disable Exception
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Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1
Transition address: VBR + H'0000 0100
Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR, and the contents of R15 are saved in SGR.
Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F (but
excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L
instructions corresponding to FPUL and FPSCR.
General_fpu_disable_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000800;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 6.0, 07/02, page 151 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
