Effective address
31 26 25
13 12 10
5 4
2
0
RAM area
judgment
Longword (LW)
selection
[12:5]
OIX
ORA
[13]
Entry
selection
22
Address array
(way 0, way 1)
9
Data array (way 0, way 1)
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
3
LRU
Tag address
U
V
0
MMU
19
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
511
19 bits
1 bit 1 bit
1 bit
Compare Compare
way 0 way 1
Write data
Read data
Hit signal
Figure 4.3 Configuration of Operand Cache (SH7750R)
Rev. 6.0, 07/02, page 101 of 986