Effective address
31 26 25
13 12 11 10 9
5 4 3 2 1 0
RAM area
determination
[11:5]
OIX
ORA
[13]
[12]
22
Longword (LW) selection
Data array
9
3
Address array
Tag
U
V
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
0
MMU
19
511
19 bits
1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Write data
Read data
Hit signal
Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S)
Rev. 6.0, 07/02, page 100 of 986