3.7.5
UTLB Data Array 1
UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data
array are specified in the data field.
In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry
is selected by bits [13:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits
[6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0].
The following two kinds of operation can be used on UTLB data array 1:
1. UTLB data array 1 read
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
2. UTLB data array 1 write
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
31
24 23
14 13
8 7
0
Address field
Data field
1 1 1 1 0 1 1 1 0
E
3130 29 28
10 9 8 7 6 5 4 3 2 1 0
PR C D
PPN
V
PPN: Physical page number
V: Validity bit
PR: Protection key data
C: Cacheability bit
SZ SH WT
E: Entry
SZ: Page size bits
D: Dirty bit
SH: Share status bit
WT: Write-through bit
: Reserved bits (0 write value, undefined
read value)
Figure 3.17 Memory-Mapped UTLB Data Array 1
Rev. 6.0, 07/02, page 92 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
