3.7.2
ITLB Data Array 1
ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are
specified in the data field.
In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry
is selected by bits [9:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit
[6], C by bit [3], and SH by bit [1].
The following two kinds of operation can be used on ITLB data array 1:
1. ITLB data array 1 read
PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to
the entry set in the address field.
2. ITLB data array 1 write
PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry
corresponding to the entry set in the address field.
31
24 23
10 9 8 7
E
0
Address field
Data field
1 1 1 1 0 0 1 1 0
3130 29 28
10 9 8 7 6 5 4 3 2 1 0
PPN
V
C
PR SZ
SH
PPN: Physical page number PR: Protection key data
V: Validity bit
E: Entry
C: Cacheability bit
SH: Share status bit
SZ: Page size bits
: Reserved bits (0 write value, undefined
read value)
Figure 3.14 Memory-Mapped ITLB Data Array 1
Rev. 6.0, 07/02, page 89 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
